---

Fiber optic connectors can be divided into three groups: simplex, duplex and multiple fiber connectors.

Simplex connector means only one fiber is terminated in the connector. Simplex connectors include FC, ST, SC, LC, MU and SMA. Duplex connector means two fibers are terminated in the connector. Duplex connectors include SC, LC, MU and MT-RJ. (Note: SC, LC and MU connectors have both simplex and duplex version).

The industry trend has been to adopt the MT-RJ interface for low data rate (below 1 Gbit/s), multimode applications, and the LC for high data rate (above 1 Gbit/s) applications, both single-mode and multimode (mainly using SX transceivers). Transceiver development has been facilitated by ad hoc industry standards or multisource agreements (MSAs), which govern transceiver package dimensions, electrical interfaces and host board layouts, card bezel design, mechanical specifications (including insertion, extraction, and retention forces), and transceiver labeling. The original MSA for SFF transceivers was supported by 15 companies, including Agilent, IBM, Lucent, Siemens/Infineon, Amp/Tyco, and others. It defined a pin through hole device with two rows of five pins each.

Recently, a second MSA has been approved by the member companies and defines a pluggable transceiver that mates with a surface mountable card receptacle. These small form factor pluggable (SFP) transceivers make it possible to change the optical interface at the last step of card manufacturing, or even in the field, to accommodate different connector interfaces or a mix of SX and LX transceivers. This should make it easier to adjust optical interface characteristics on future system designs, in much the same way that the GBIC transceiver did for the SC Duplex interface (in fact, the SFP is sometimes known as a "mini-GBIC"). The SFP connector has 20 signal connections and provides three additional functions in addition to the original 10 SFF signal pins. These new functions include module definition pins that specify a serial ID indicating the type of transceiver function (such as LX vs. SX transmitters), a data rate select function (such as 1 Gbit/s vs. 2 Gbit/s), and a transmitter fault signal.

MOD-DEF 0,1,2 are the mode definition pins.

• MOD-DEF 0 is grounded by the module to indicate that the module is present
• MOD-DEF 1 is a clock SCL line for the I²C identification EEPROM
• MOD-DEF 2 is a data SDA line for the I²C identification EEPROM
  

A metal receptacle, sometimes called a cage or a garage, is surface mounted to the printed circuit board to accept the pluggable transceivers. In addition to providing easy replacement and reconfiguration of the transceiver interface, this offers several other advantages. The transceiver is often the only pin through hole component on a modern card design; the SFP cage allows the elimination of extra manufacturing processing steps and potentially reduces cost. By removing the optical components from the soldering process, the SFP should provide improved reliability of the optics and permits the use of higher soldering temperatures. (This may be important as environmental regulations require future lead-free solders with higher process temperatures.) SFP connector and cages are employed to interface copper or fiber-optic pluggable transceivers and cable assemblies to host equipment. Mounted on the host PCB and protected by a low-profile metal cage, the SFP connector system is designed to guide and support the industry-compliant mating modules.

The industry has recently developed enhancements to the SFP MSA, known as SFP Plus (SFP+), which is intended to achieve higher data rates, lower cost, and improved thermal performance. As of this writing, this specification has not been finalized for public release, although many companies are now designing compliant transceivers. Although SFP+ is applicable to the same application set as SFP, and includes both copper and optical interfaces, it is particularly intended to support high data rate links such as 8.5 and 10.52Gbit/s Fibre Channel, 10Gbit/s Ethernet (10.31 Gbit/s links, or 11.1 Gbit/s links using forward error correction, including 10GBase SR, LR, and LRM), SONET OC-192 (9.95 Gbit/s), and G.709 "OTU-2" (10.7 Gbitls). The specification is similar to SFP, with a common form factor and optical interface. There is a new electrical interface specification, called SFI, designed to handle higher data rate performance; this is defined in SFP specification 8431. In particular, the jitter budgets are planned to be somewhat tighter for SFI than for a standard SFP interface (though not as restrictive as the XFI interface). We also note that SFP+ has not defined a data rate selection pin, meaning that SFP+ transceivers may be compatible with lower data rates but not necessarily compliant with the older specifications.

The industry has recently developed enhancements to the SFP MSA, known as SFP Plus (SFP+), which is intended to achieve higher data rates, lower cost, and improved thermal performance. As of this writing, this specification has not been finalized for public release, although many companies are now designing compliant transceivers. Although SFP+ is applicable to the same application set as SFP, and includes both copper and optical interfaces, it is particularly intended to support high data rate links such as 8.5 and 10.52Gbit/s Fibre Channel, 10Gbit/s Ethernet (10.31 Gbit/s links, or 11.1 Gbit/s links using forward error correction, including 10GBase SR, LR, and LRM), SONET OC-192 (9.95 Gbitls), and G.709 "OTU-2" (10.7 Gbitls). The specification is similar to SFP, with a common form factor and optical interface. There is a new electrical interface specification, called SFI, designed to handle higher data rate performance; this is defined in SFP specification 8431. In particular, the jitter budgets are planned to be somewhat tighter for SFI than for a standard SFP interface (though not as restrictive as the XFI interface). We also note that SFP+ has not defined a data rate selection pin, meaning that SFP+ transceivers may be compatible with lower data rates but not necessarily compliant with the older specifications.

A revised SFP+ mechanical specification (sometimes known as "improved pluggable form factor"), including thermal and electromagnetic compatibility, is also available through SFP specification 8432. In particular, SFP+ defines two classes of maximum power dissipation: class I (up to 0.8 W) and class II (up to 1.5 W). The class II transceivers are intended for DWDM and telecom applications (single-height cage with cooled optics). The SFP+ transceivers are backward compatible with most (but not necessarily all) SFP cages implemented according to the SFF-8074i specification. However, in this case the full benefit of SFP+ improvements in electromagnetic susceptibility and other parameters may not be achievable.

At this writing, some important practical questions remain, such as whether the 8G and 10G implementations can be realized with a common transceiver. Although they will use the same optics, 8G Fibre Channel needs to be backward compatible with at least 2 previous generations of the Fibre Channel standard (4G and 2G) using 8B/10B encoding. (10G Fibre Channel uses a different encoding scheme and is therefore not backward compatible with lower data rates.) By contrast, to accommodate the full range of Ethernet standards options including FEC, the 10G transceiver must operate over data rates ranging from 10.3 to 11.1 Gbit/s using 64B/66B encoding. The use of a single electrical receiver design (linear vs limiting) for 10G remains a design issue, as well as the question of whether clock and data recovery should be more closely integrated into the transceiver.

Recent interest has been shown in further increasing the transceiver port density for optical datacom applications, particularly blade servers, as well as finding a cost effective way to increase aggregate data rates beyond 10Gbit/s. One approach is the quad small form factor pluggable (QSFP) multisource agreement, originally announced in March 2006 and finalized in December 2006 following a period of public comment on the proposed specifications. The QSFP MSA is currently endorsed by over 20 companies. QSFP defines an integrated, hot pluggable, four-channel optical transceiver, designed to replace four standard SFP modules in a space only 30% larger than a single SFP. The resulting port density is three times higher than conventional SFP designs; various stacked and ganged configurations are possible to achieve increased port density, and presumably lower cost per port (a minimum of 21 mm center-to-center spacing is allowed for adjacent QSFP transceivers). The transceiver is a so-called z-axis pluggable module, meaning that the 38 contact electrical connector can be inserted parallel to the host circuit board without requiring additional operations such as screwing the transceiver package to the host card.

QSFP accommodates a standard MPO connector, though only 8 of the 12 available fibers are used to carry signals. Exposed portions of the optical connector or card bezel are color coded following common industry practice (beige for 850nm/multimode, blue for 1300nm/single-mode, white for 1550nm/single-mode). The MSA defines a mechanical form factor with latching mechanism similar to that used by XFI, host board electrical receptacle, and a cage to house the transceiver when it is plugged onto a host card. Digital diagnostics are provided to monitor link performance; the diagnostic interface includes the ability to set link distance parameters that identify the capabilities of the transceiver, including an option for copper QSFP implementations. QSFP uses a single 3.3 V nominal power supply, with a maximum power dissipation under 3.5 W. Various types of vendor-specific heat sinks can be attached or clipped onto the transceiver. Data rate options ranging from 100 Mbit/s to 10 Gbit/s per channel are defined (with an available rate select pin on the electrical interface) to support protocols, including Ethernet, Fibre Channel, InfiniBand, and SONET/SDH. In particular, with a potential data rate of 10Gbit/s/channel, this transceiver may provide a cost-effective implementation of 40Gbit/s links. The inherent 4 + 4 channel architecture of QSFP lends itself to increase distances supported by multilane serial I/O electrical interconnects such as PCI Express (PCIe) and InfiniBand.